VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获...

基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter

说明：  基于quartus2的jk触发器设计，内含源码和仿真图(Jk flip-flop design based on the quartus2, containing source code and simulation diagram)

本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。(The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.)

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

说明：  Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency

伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)

全加器结构描述是从设计实体的内部结构对结构体进行描述的，并给出该实体所包含的模块或元件的相互连接关系-fulladd