VHDL与源代码包

基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program )

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)

在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改，经设备验证无错误，且运行良好。

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

本人上网下载下来并调试过的，完全实现NIOS 下对SD卡读写及包括FAT16文件系统的实现，使用的是QT8.1，FPGA里实现，里面有详细接线图，是完整的一个工程，在EP2C20Q240C8里调试成功-I downloaded off the Internet and debug off, and the full realization of NIOS under the SD card reader and includes FAT16 file system implementation, using QT8.1, FPGA years to achieve, which detailed wiring diagram, is a complete one project in EP2C20Q240C8 debug in the success of

本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

papers based on distributed arithmetic.

VHDL 的4*4键盘代码-VHDL 4* 4 keyboard code

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.