VHDL与源代码包

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

对三相电压型逆变器的数学模型进行了详细的数学推导，简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

说明：  Micron公司m73a系列nand flash仿真模型及测试文件(micron m73a series nand flash simulation model and testbench)

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)

matlab code for JTAG cable checking

该项目用来测量频率。它有三个范围，其中包括 0.01 赫兹 ~ 1 Hz，1 ~ 100 Hz 和 100 ～ 10000 Hz。这样的结果将是最好的程序能自动调节到最佳的范围内。这个项目是在 Altera 软件 8.1 上进行验证。