基于ＦＰＧＡ平台，实现了直接数字频率合成。

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

简单的8个CPU，包含PDF文件。他们可以查看详细信息

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

VHDL Code For Full Adder By Data Flow Modelling

说明：  基于BP算法的LDPC译码程序，采用vhdl语言，bp算法(BP algorithm based on LDPC decoding program using vhdl language, bp algorithm)

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)

QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)

说明：  VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)