基于ＦＰＧＡ平台，实现了直接数字频率合成。

FFT with fix point 2*N

本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver

shift example for verilog

Verilog code to calculate Sobel

this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation