登录
首页 » VHDL » 有业主从PCI PCI、PCI目标是开源的,是项目的发展。

有业主从PCI PCI、PCI目标是开源的,是项目的发展。

于 2022-06-15 发布 文件大小:2.59 MB
0 172
下载积分: 2 下载次数: 1

代码说明:

内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持: 1、 对目标PCI_T进行配置; 2、 对目标进行单周期读写; 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • project_1
    说明:  简单的一个Verilog小程序,适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
    2020-06-16 22:20:01下载
    积分:1
  • FIFO
    FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)
    2010-10-11 20:35:47下载
    积分:1
  • firfilter
    FIR滤波器:自定滤波器的类型(低通,高通或带通)、设计指标(通带截止频率、通带波纹、阻带截止频率、阻带衰减) 1、根据指标选择合适的窗函数,用窗口设计法设计符合指标的FIR滤波器;并验证其性能是否满足预定指标。 (FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, stopband cutoff frequency, stopband attenuation) 1, according to indicators choose the right window function, using the window design method of FIR filter designed to meet the targets and verify that its performance meets the set targets.)
    2010-01-13 19:14:21下载
    积分:1
  • Examples of VHDL language, including a variety of logic gate structure.
    vhdl 语言实例,包括各种逻辑门的构造。-Examples of VHDL language, including a variety of logic gate structure.
    2022-08-08 14:03:44下载
    积分:1
  • A8255的vhdl源代码,比较简单的一个
    A8255的vhdl源代码,比较简单的一个-Vhdl source code of A8255
    2022-05-07 14:31:39下载
    积分:1
  • Verilog languages with four arithmetic logic unit ALU, functional reference to 7...
    用verilog语言编写的4位算术逻辑单元ALU,功能参考74181,包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document
    2023-07-06 11:15:03下载
    积分:1
  • usbhostslave
    说明:  USB主机和设备的verilog代码,实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)
    2005-09-13 11:34:09下载
    积分:1
  • Masseffect-3---Jane-Shepard
    超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載(Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download)
    2013-09-13 13:33:13下载
    积分:1
  • shouhuoji.vhd
    自动售货机程序(Vending machine procedures)
    2008-04-05 22:08:58下载
    积分:1
  • VMD642_CPLD
    本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
    2013-09-13 13:59:52下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载