典型的例子，从互联网上下来，希望对大家有用，

cpu与GPU协同计算一个同时支持GPU与CPU的MapReduce框架实现(cpu and GPU collaborative computing)

说明：  FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．-Four dynamic refresh digital tube display, VERILOG code, with detailed notes in Chinese.

韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验(Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and keystrokes 4 experimental statistics)

本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA" s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.

一款非常实用的8051IPcore,本人现在做soc的控制部分就是它。(A very useful 8051IPcore, I now control part of the soc is doing it.)

基于FPGA的7x7块交织器设计，程序分交织、解交织两部分，并在QUARTUS II 9.0 下仿真通过，内附模块详细端口说明及仿真分析文件。

本文件是周立功试验开发板的配套资料，容易学会-This document is ZLG test development board supporting information, easy to learn

3 Digit BCD to 7 segment indicator decoder

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)