这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来...

Use full for knowing board details while making projects on FPGA and matlab simulations

FPGA上用verilog写的SPWM控制程序，完美运行！自由调试，毕设内容，十分宝贵(The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable)

altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success

vhdl code for cyclic cfft control

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)

说明：  一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调(FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable)

这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)