用FPGA实现GPS数据解析，Verilog测试通过

D-flip flop vhdl implement code

小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)

约束所有时钟（包括你的设计中特有的时钟）对准确的时序分析结果而言是必不可少的。Quartus II TimeQuest Timing Analyzer为各种各样的时钟配置和典型时钟提供许多SDC命令。(Constraining all clocks, including the clocks unique to your design, is essential for accurate timing analysis results. The Quartus II TimeQuest Timing Analyzer provides many SDC commands for a variety of clock configurations and typical clocks.)

PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)

基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

Verilog 语言写的控制 DAC8568 的模块，DAC8568 是SPI接口。(Verilog language used to write the control module DAC8568, DAC8568 is SPI interface.)

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

FPGA的驱动并行接口的DAC程序，效率较高。(FPGA-driven parallel interface of the DAC process more efficient.)