用FPGA实现GPS数据解析，Verilog测试通过

实现了光OFDM模块的各个功能，同时仿真分析了OFDM的载波幅度谱、相位谱、每个载波对应的时域信号、整个时域/频域的OFDM、每个接收符号的分布图。计算了相位差等等(To achieve the various functions of the optical OFDM module, the simulation analysis of the the the OFDM carrier amplitude spectrum and phase spectrum, and the time domain signal corresponding to each carrier, the whole time domain/frequency domain OFDM, each reception symbol maps. Calculated phase difference)

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

LDPC编译码，最新一代纠错码技术，自带校验矩阵，数据程序内带测试数据

正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)

说明：  verilog 版本，Xilinx玩转USB3.0，LVDS接口(verilog version,Xilinxplay with USB3.0,LVDS)

主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

此程序为32位的CRC校验程序，我们利用verilog语言较容易的编写串行的CRC校验程序，但是在一些情况下需要并行的处理数据，在此编写了4位并行的CRC校验程序。 包括了CRC主程序和测试程序。

这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)