SDRAM程序控制器

verilog lcd2864 适合初学者(verilog lcd2864 )

AMBA_APB verilog code

使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形(use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms)

说明：  采用Verilog编写AD9467配置文件(Using Verilog to write ad9467 configuration file)

说明：  对delta sigma进行设计，实现delta sigma ADC的设计(this is use for delta sigma adc ,and design and achieve adc)

说明：  基于FIR设计的100阶数字滤波器，选择的矩形窗(100 - order digital filter based on FIR)

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))