Dc to use a very good book a very good use of books dc

polyphase fir dilter

真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)

74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中(74ls161 language based on the realization of verilog source package in compressed folder hdl)

代码为ahb interface ，用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)

verilog spi file with testbench

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真(DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL)

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)