用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。...

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)

说明：  多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。(library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all )

SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

基于FPGA的FFT处理器的实现，适合做fpga的工程技术人员参考-FPGA-based realization of the FFT processor, suitable for the engineering and technical personnel fpga reference

Mentor Graphics ModelSim User s Guide Software v6.3g

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )

altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)