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一个完整的设计DE2_project,希望对大家有所帮助,谢谢ok
一个完整的设计DE2_project,希望对大家有所帮助,谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok
- 2022-04-18 05:42:24下载
- 积分:1
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LCD12864
LCD12864的显示程序,使用的是verilog语言编写的显示程序,为PDF文档(LCD12864 display program, using Verilog language display program, as a PDF document)
- 2013-05-11 09:53:44下载
- 积分:1
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用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。...
用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.
- 2022-05-22 13:12:54下载
- 积分:1
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viterbi_msk
连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)
- 2012-10-29 23:07:38下载
- 积分:1
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1pps
说明: fpga程序,产生1pps脉冲信号,使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:01下载
- 积分:1
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A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, an...
非常有用的IP核资源,里面包含了JTAG,MEMORY,PCI,SDRAM和USB1.1等内容,期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
- 2022-03-03 12:55:22下载
- 积分:1
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vhdl的一个串行序列信号发生器的设计与实现
vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation
- 2022-04-24 02:34:50下载
- 积分:1
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功率门控IEEE论文可为IP核的实现充分利用
ieee paper on power gating and can be use full for implementing on ip core
- 2022-02-03 18:58:04下载
- 积分:1
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verilog-axi-master
说明: Verilog AXI Components Readme
GitHub repository: alexforencich verilog-axi
- 2020-11-04 14:39:51下载
- 积分:1
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Four-FPGA-design-techniques
FPGA设计的四种常用思想与技巧,包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)
- 2012-04-22 22:39:57下载
- 积分:1