本代码实现了486总线的功能，初学者可以借鉴学习

基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.

说明：  THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)

此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

基于FPGA的画中画处理PDF技术文档，采用SD卡里图片读出来做为底图，然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation )

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)

Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles