登录
首页 » VHDL » 温度码到二进制吗的转换的verilogHDL代码。

温度码到二进制吗的转换的verilogHDL代码。

于 2022-02-28 发布 文件大小:1.29 kB
0 194
下载积分: 2 下载次数: 1

代码说明:

温度码到二进制吗的转换的verilogHDL代码。-Temperature code to do the conversion of binary code verilogHDL.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • stopwatch_if
    用IF语句实现秒表功能的代码,显示范围在000至99.9.(Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.)
    2015-07-13 22:33:36下载
    积分:1
  • generate-coordinates
    使用VHDL编写语言,巧妙的利用计数器和循环输出一个坐标系,由于VHDL出现负数比较麻烦,全部由正数代替,输出一个原点在中心,半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)
    2013-08-28 11:03:46下载
    积分:1
  • test1
    利用matlab,对偏振控制器进行仿真,最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)
    2013-04-07 10:42:15下载
    积分:1
  • tPad_Camera
    tPad DE2-115/70开发板可用的摄像头采集、显示程序,QT10.0以上环境可用,原装代码,可以进行修改加以使用,如使用到倒车影像系统中,视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)
    2020-07-09 19:58:55下载
    积分:1
  • C-V2X-master
    LTE is an abbreviation for Long Term Evolution.
    2019-06-29 01:08:09下载
    积分:1
  • 华为经典FPGA设计全套入门技巧
    华为FPGA设计全套资料,学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)
    2019-04-02 13:54:48下载
    积分:1
  • 基于DDS的DA正弦波输出
    Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until
    2022-01-26 04:06:16下载
    积分:1
  • air
    空调温控电路有限状态自动机, 有TEMP_HIGH和TEMP_LOW 分别与传感器相连用语检测室内温度.-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
    2022-04-25 13:00:13下载
    积分:1
  • 自已写的一个16X16的乘法器,速度比较慢。初学者练习练习!
    自已写的一个16X16的乘法器,速度比较慢。初学者练习练习!-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
    2022-07-02 12:25:49下载
    积分:1
  • Lossless_Compression_Method_for_Bayer_Image_and_FP
    描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)
    2010-08-31 12:24:49下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载