温度码到二进制吗的转换的ｖｅｒｉｌｏｇＨＤＬ代码。

用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.

32 bit RISC Processor with 3 stage pipeline

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

说明：  BUS documentation and map reffereces

quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容

说明：  基于labVIEW，控制电机等工作实例，程序基本完整(Based on labVIEW, control motor and other working cases, the program is basically complete)

本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)

自己编写的C++的类的测试程序，有详细的注注释，对初学者有很大帮助！！！(The own written C++ class test program, detailed annotation of Note of great help for beginners! ! !)