for Dictyophora board, in the way of achieving LCD clock function.

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents

数字电路与逻辑设计实验编程，包含多功能电子钟程序，实用，简易(Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple)

说明：  uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)

说明：  实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

Dynamic Power Management for the Iterative Decoding of Turbo Codes

this program performs multiplexing and demultiplexing

1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)

48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)