HDLC协议

用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.

自己在ISE下用VHDL写的UART，简单，易懂(in ISE using VHDL was the UART, simple, understandable)

利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.

这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended

图像采集、存储控制verilog源代码(Image acquisition, storage, control of Verilog source code)

adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)

数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

说明：  简单的vhdl的四位并串转换程序，可以实现数据的并串转换(Simple vhdl string of four and the conversion process, can convert the data and the string)

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)