HDLC协议

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)

有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.

说明：  QSPI_FLASH_MODEL 可以设计时前端仿真使用(QSPI?_Flash_Model can be used in front-end simulation at design time)

Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!-This book is very important for a designer who wants to design a great digital circuits!

基于FPGA的1553B总线编码解码器的设计-1553B Bus FPGA-based codec design

图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of

this files in Quartus2 are fulladder

（1）用HDL设计一个多功能数字钟，包含以下主要功能：精确计时，时间可以24小时制或12小时制显示； （2）日历：显示年月日星期； （3）能用QuartusII软件仿真；