powerlink开源的最新全部源码

对NC Verilog的基本介绍，详细的图解，非常适合初学者使用，一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document

这本书是夏宇文老师在几年前编写的，非常是和初学者，里面有哦对verilog 的详细讲解(a book write by xiyuwen ,This book provides a detailed explanation of verilog )

标准的异步串口通讯设计程序――基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

吠陀乘数

该代码实现出租车计费功能，例如起步价为5元，按住相关控件后，每隔五秒，计数将加1，实现类似于开车时计费的功能，当松开按键后，计费也将停止。。。。

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA