基于VHDL数字频率计

design cpu 16 bits by verilog HDL.

MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！-MAX531 serial DA chip VHDL driver, I shall be in the actual project tested!

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

基于 CPU 的精确计时器，时钟频率越高，计时越准(Based on the exact CPU timer, the higher clock frequency, the more time-quasi-)

一个数码管的驱动开发程序，程序完备，可以直接使用，在开发板上使用时注意改变引脚(A digital control of the driver development program, the program is complete, can be used directly, when used in the development of attention to change the pin board)

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)

Program for simulate a prtsc

说明：  利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .)

基于vhdl可用的数字频率计，误差较小，精准度较高。文件中还包含了与arm的通信模块、

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)