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用Verilog做的SD卡控制器(有详细的注释)
SDIO 接口,实现SD卡的控制器功能,带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)
- 2020-06-16 22:00:01下载
- 积分:1
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EDA应用中RAM具体定义实例,供大家学习和写程序参考之用
EDA应用中RAM具体定义实例,供大家学习和写程序参考之用-EDA applications, examples of the specific definition of RAM, for everyone to learn and write programs for reference
- 2022-08-18 02:44:17下载
- 积分:1
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三角波的产生
这是源代码,该代码为三角波的一代,在 VHDL 写。欢迎下载。谢谢你的支持。
- 2022-08-03 08:08:41下载
- 积分:1
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PWM
基于FPGA的PWM控制器设计,包含ADC0820模块,按键扫描,PID,PWM控制器等模块,VHDL语言完成,已仿真通过(PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation)
- 2016-05-01 15:05:58下载
- 积分:1
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imports
displayport 参考设计,可以对比自己工程做验证,另有参考设计XAPP1178未找到,采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分:1
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fpalign_struct
floating point alignment
- 2013-03-11 16:53:31下载
- 积分:1
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这是可编程逻辑器件(CPLD)初学者的入门级文章,仅供参考。...
这是可编程逻辑器件(CPLD)初学者的入门级文章,仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
- 2022-01-22 10:28:59下载
- 积分:1
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基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出...
基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output
- 2023-03-31 21:30:04下载
- 积分:1
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frame_syn
通信系统中数据的传输以帧为单位,在FPGA中帧头检测是通信系统中的一部分,该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)
- 2014-08-27 16:02:54下载
- 积分:1
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Verilog_Ip_RAM
说明: altera ram ip教程。对RAM进行读写操作,写32个数据到RAM中,再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)
- 2020-08-17 11:38:21下载
- 积分:1