FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好

关于FPGA针对LCD资源配置，及相关电路层次关系(LCD FPGA)

It is the FSM implemented in Xylinx 14.7 on FPGA

CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7

单片机4路ad模数转换数码管动态显示程序(4-way ad microcontroller analog to digital conversion digital tube dynamic display program)

i2s串行线广泛用于音频通信中,这里包括了master和slave的代码.-i2s serial lines widely used in audio communication, here including the master and slave codes.

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

基于matlab的BOC仿真程序，包含BOSK调制等。(Based on the matlab the BOC simulation program, contains modulation BOSK.)

对三相电压型逆变器的数学模型进行了详细的数学推导，简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

cic设计 verilog verilog(cic verilog design verilog)