异步FIFO的设计 包括testbench 已调试成功

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.

说明：  vhdl code for full adder

基于DE2-70开发板的VGA接口实现程序，可在VGA屏幕上显示800*600分辨率的图像，刷新频率60Hz

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)

内置自修复分析仪

VHDL servo control from technique of Pulse Width Modulation (PWM )

基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)

Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。(Verilog code, suitable for beginners to learn, is based on the DE2 platform code.)

/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息. // 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测. // 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电 // 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)