用VHDL语言编写的一个16分频器，也在修订过程中任意2…

平坦度检测中的高度检测算法，使用ISE开发环境，语言为VHDL，平台是XC3S4-a vhdl_program used for flat detect

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.

timblogiw.c timberdale FPGA LogiWin Video In driver.

AD7266的Verilog驱动程序,已仿真通过,可直接在EDK下使用.

这是介绍嵌入式开发相关的资料。有总线与内存的操作-introduced Embedded Development relevant information. Bus and a memory operation

Clock Divider, divfactor of 18

VHDL Language Reference courses part4

verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)

说明：  Verilog code for implementing simple ALU.