用VHDL语言编写的一个16分频器，也在修订过程中任意2…

Verilog语法教程，适合初学者，详细(Verilog instruction book)

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)

伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

this is a simulation fm in simulink mathlab this is one program with pll

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

code for booths multiplier

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

RobustVerilog生成verilog工具(RobustVerilog version)

黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)