-
Quartus a complete design examples, examples from installation to completion, th...
quartus一个完整的设计例子,从安装到实例完成,仿真等全过程,适合从0开始的初学者-Quartus a complete design examples, examples from installation to completion, the entire process of simulation, etc., suitable for the beginner to start from 0
- 2022-07-26 09:40:40下载
- 积分:1
-
qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分:1
-
aFifo
verylog语言编程,为异步flipflop的程序。具有数据传输功能,数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)
- 2007-08-28 10:26:03下载
- 积分:1
-
yuanchengxu
基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)
- 2011-11-19 13:36:54下载
- 积分:1
-
IDT7005
双端口静态RAM的VHDL程序,具体芯片型号为IDT7005(DUAL-PORT
STATIC RAM)
- 2014-04-03 11:40:53下载
- 积分:1
-
PCIE
xilinx spartan6的pcie pio源代码(xilinx spartan6 pcie pio demo)
- 2020-11-25 14:39:32下载
- 积分:1
-
DSP-keshe
设计题目:基于MATLAB的FFT算法的设计
设计内容:
所设计的FFT算法应完成以下功能:
(1)在MATLAB环境下编写FFT算法(不调用系统现有函数);
(2)实现对选定图片进行FFT计算、还原(IFFT计算),并与系统FFT函数做对比,进行分析;
(3)设计GUI界面。
(Design topics: content based on the the MATLAB FFT algorithm design design: the design of the FFT algorithm should perform the following functions: (1) the FFT algorithm written in MATLAB environment (do not call existing function of the system) (2) to achieve the selected picture for FFT calculation, restore (IFFT calculation) system FFT function analysis (3) design GUI interface.)
- 2013-04-09 16:51:00下载
- 积分:1
-
Combined unit GPS clock synchronization detection unit merger GPS synchronized c...
合并单元内GPS同步时钟的检测
合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
- 2023-05-04 14:30:04下载
- 积分:1
-
CNT4
说明: 4位二进制加法计数器的两种不同VHDL的描述,与比较。(4-bit binary addition of two different counter VHDL description, and more.)
- 2010-04-13 22:20:44下载
- 积分:1
-
binary LDPC DECODER
二进制LDPC解码器:
- 2022-05-31 06:59:45下载
- 积分:1