基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！

To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.

用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.

基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note

3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)

SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code

电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti

4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.