verilog file , FPGA controll vga display

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)

光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)

VHDL Language Reference courses part4

有用的VHDL源代码-useful VHDL source code

crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)