Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...

8对于输入密码锁的键，假设重置后七个灯显示" 0"，并且使用sw1、sw2、sw3 3，只需按任意sw1、sw2、sw3，将使七个灯显示值相加" 1

用于串行到并行数据转换器的VHDL代码；当输入数据是串行的时，该代码是用于许多应用程序的位到字节转换的VHDL代码形成代码使用基于FPGA的LUT和D-RAM来存储数据，然后用时钟推送字节对齐的数据。

verilog实现闪烁灯和流水灯dechengxu-verilog liushuideng shanshuodeng chengxu

用FPGA控制1602型液晶显示，显示一行英文语句。-show

CAN VHDL Code. Behavioral implementation of CAN bus interface.

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

rda1846 + pic18f2552 usb circuit schematic.

AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)