VHDL_modelling_guidelines是vhdl建模开发的指导资料

利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤(rs code in FPGA)

基于FPGA的数字电压表 两种方案 一种VHDL一种Verilog(Digital voltmeter based on FPGA)

ethernet 10 0M MAC-ethernet MAC 10,100 M

ARM+FPGA JTAG(二合一)原理图与PCB(ARM+ FPGA JTAG (combined) schematic and PCB )

HDMI协议的Verilog实现，通过对RGB三个通道分别进行TMDS编码完成，纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。-Using VHDL language, and music performance procedures, examples of songs as

VHDL与Verilog的比较-VHDL and Verilog comparison

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)

四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through