VHDL_modelling_guidelines是vhdl建模开发的指导资料

VHDL教学的经典之作，大家学习必看的书籍。-VHDL teaching classic, must-see U.S. study books.

vhdl adder with two input 4-bit and output of 4 bits and carry

BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display

SDR SDRAM 控制器的源代码 altera公司的(source code from altera)

2. You may use this core in any way, be it academic, commercial, or -- military. Modified or not.-2. You may use this core in any way, be it academic, commercial, or-- military. Modified or not.

vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange

计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)

verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code