10进制计数器的VHDL描述必须实验

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)

频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)

Altera DE1平台的数字密码锁设计，可以驱动VGA显示(Altera DE1 platform digital password lock design, can drive VGA display)

一个非常好的dc使用书籍 一个非常好的dc使用书籍-Dc to use a very good book a very good use of books dc

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。 数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。 读者还可以通过增加小时的计时功能，实现完整的跑表功能。-A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.

说明：  光栅尺FPGA调试程序，本人亲自调试保证可用(Grating ruler FPGA debugging program)

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

自动白平衡的verilog实现 通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )