VHDL语言设计；功能描述：键盘扫描，不包含去抖电路

Priority encoder in VHDL.

基于Verilog的串口通信源码 ，实现串口通信功能(Verilog source code based on serial communication)

说明：  4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。 设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。 输入：连续脉冲，逻辑开关；输出：七段LED。 (4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.)

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

提供了100个vhdl硬件编程语言的例子,由简单到复杂-100 provides a hardware programming language VHDL examples, from simple to complex

8051内核的Verilog程序实现，完成普通的单片机8051内核功能.包含综合后文件和测试文件(The 8051 kernel Verilog program complete ordinary microcontroller 8051 kernel function. Contains comprehensive post files and test files)

很不错的资源哦，这是我在实验室当年总结的关于nios timer的程序段(nios timer)

说明：  将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)

自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone"s attention.

FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)