VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈

DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)

逐步演示试用modelsim建立仿真的过程，初学者应该看看(Step by step demonstration of the trial to establish modelsim simulation process, beginners should look at the)

vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)

AES算法部分模块行位移列变换以及主题程序加密解密(AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program)

周立功sopc教程的视频资料，适合广大自学者学习-ZLG sopc video tutorial is suitable for the general self-learners to learn

switching the lights debouncing , toggle

fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 (fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)