VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈

用Verilog实现的呼吸灯，用Verilog实现的呼吸灯(Verilog huxideng)

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency

entity or1 is(a,b:in std_logic;y:out std_logic);architecture dataflow of or1 isbeginy

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

这是一个项目，设计一个计数器和 vhdl 语言文本液晶屏上显示。为了文本液晶屏上显示我们都用 vhdl 语言设计了液晶显示控制器。