VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈

3-8译码器地简单实现，采用QUARTUSii5.0环境编译-3-8 decoder to realize a simple, using the compiler QUARTUSii5.0 environment

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

VHDL开发环境，电梯控制系统，实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role

一些常见的小模块，自己写的，可能不是特别好，仅供参考，主要是分频器、计数器和数码管的显示

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

sdram控制器的开发程序，还有文档，可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)

verilog motor control