through CPLD to eight parallel data into serial data and methods can be used I2C...

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

an example HDL-Core with any basic gates.

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new design

用VHDL语言设计篮球24秒可控计时器功能说明：1.具有24秒计时、显示功能；              2.设置外部按键，完成清零、暂停、恢复控制；              3.24秒倒计时，时间间隔为1s；               4.时间到后发出报警信号，并在3s后解除。

emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

UDP / IP上的Spartan3E以太网通信通过斯巴达3E发送UDP数据包到/从我的电脑。

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)