-
关于VHDL编程的教程,比较系统的讲解,很有用的书
关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL
- 2022-01-26 14:49:07下载
- 积分:1
-
数字秒表设计
资源描述这个秒表特点是计数到59分59秒9,并且有可以让计数暂停和清零。采用了二分频,六进制和十进制组合,加上扫描电路设计而成的。
- 2022-08-24 22:31:41下载
- 积分:1
-
used in the preparation of Verilog FLEX10K achieve simple CPU
用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
- 2022-03-25 10:21:37下载
- 积分:1
-
BCD
BCD码减法实现程序,非常完整,采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)
- 2010-08-04 16:43:26下载
- 积分:1
-
shumagua
通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made into a single-chip digital clock program)
- 2013-10-27 12:30:04下载
- 积分:1
-
刚写的一个44键盘程序,调了好多天才调出来,给大家提供参考。...
刚写的一个44键盘程序,调了好多天才调出来,给大家提供参考。-Just write a 44 keyboard program, tune out of tune a lot of talent to give you a reference.
- 2022-08-09 01:20:18下载
- 积分:1
-
VHDL语言,设计一个在DE2平台的8个七段数码管上循环显示HELLO的程序
VHDL语言,设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序,采用按键控制循环的速度,慢速循环时间间隔为1S,快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)
- 2020-07-08 20:28:56下载
- 积分:1
-
SystemOfTaxiFeeBasedOnVerilogHDL
摘 要:以上海地区的出租车计费器为例,利用Verilog HDL语言设计了出租车计费器,使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化,下载到EPF1OK10TC144—3芯片中,可应用于实际的出租车收费系统。
关键词:Verilog HDL;电子自动化设计;硬件描述语言;MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分:1
-
verilog_422
标准RS422 Verilog源代码, 传输波特率可以修改, FPGA上可以工作(Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA )
- 2021-04-06 14:29:02下载
- 积分:1
-
JIAOTONGDENG
用VERILOG实现 交通灯控制,且运行正确,希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分:1