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str
these are verilg prgms
- 2012-12-05 18:12:51下载
- 积分:1
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程序采用VHDL:频率合成DDS主要调用LPM,
程序用VHDL实现:
频率合成,DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分:1
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ahb_interface
AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)
- 2020-11-23 10:39:35下载
- 积分:1
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7-5
基于FPGA的ip核FIR低通滤波器,实现滤波功能,简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)
- 2020-10-05 11:47:38下载
- 积分:1
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32bit_multiply
包含32为乘法器的设计,用verilog语言实现,包括booth编码的实现,booth乘法器的实现,3_2压缩器的实现,4_2压缩器的实现,华伦斯树的实现,以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)
- 2015-01-18 21:20:48下载
- 积分:1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立,能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分:1
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Electronic design automation in the conversion of traffic signals on the realiza...
电子设计自动化中关于交通信号的转换的实现程序,基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language
- 2023-05-04 11:45:03下载
- 积分:1
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shuzi
讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form
)
- 2011-12-17 00:55:01下载
- 积分:1
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Documentation Of Digital Electronic Systems With VHDL from US DOD.
Documentation Of Digital Electronic Systems With VHDL from US DOD.
- 2022-05-09 12:50:24下载
- 积分:1
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实现了简单的电子表功能,是24小时,用VHDL所编写的,quartus ii 7.2...
实现了简单的电子表功能,是24小时,用VHDL所编写的,quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2
- 2023-05-19 01:30:03下载
- 积分:1