mimasuo

these are verilg prgms

程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM

AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)

基于FPGA的ip核FIR低通滤波器，实现滤波功能，简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

Documentation Of Digital Electronic Systems With VHDL from US DOD.

实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2