RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

DE2 altera board vhdl design

我自己当初用来求解arctan 暂时没有搞成ip形式 搞好了还要传git 这个代码还没有搞好，因为急需要下载东西 如果感兴趣可以联系我 邮件(this is a not full wrappered code very crude use chebyshev to caculate arctan function i m urgent to download a model from pudn so i do this.)

axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)

通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用-Communication and Control through the vga display colorful provisions quartus compiled through the procedures that can be used

用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-VHDL language using a control program, the main function is to input code synchronization, and frame signals output word

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures