RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write

FGAP控制模拟量输出芯片DAC8812(FGAP control analog output chip DAC8812)

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

说明：  用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )

内容太短。注意请： 代码没有很好的描述将被删除，你不会得到任何点。请描述一下更好地获得更多积分。

可YCrCb2RGB集成模块（Verilog）采用三行，它们简单的做分数运算，有流水线技术

基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

fpga hardware hevc implementation

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

verilog ad9777 ad芯片的配置程序，SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)