This is an 16 bit adder using vhdl

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

说明：  国外的CIC补偿滤波器设计文件，非常有用(Abroad, CIC compensation filter design files, very useful)

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~

说明：  基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)

EP2C5T144 驱动 LCD1602液晶(LCD1602 LCD driver EP2C5T144)

-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn

verilog ad9777 ad芯片的配置程序，SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)

verilog code for 3 bit sequence detector

mpeg-2 crcr32计算的代码，采用verilog编写，验证通过(mpeg-2 crcr32 caculate)

红色飓风3S700AN开发板UART测试例程(Red Hurricane 3S700AN ​ ​ development board UART test code)