乘法器的vhdl语言描述.本人调试已经通过

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

modbus的fpga实现。opencores上最新版本。使用fpga实现，可以大大提高响应速度，对其功能进行模块化。(modbus of fpga implementation. opencores the latest version. Use fpga implementation, can greatly improve the response speed, its function modularity.)

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

Implementation of Serial Infrared decoder for low-speed IrDA communications.

单相的主动式电压质量控制器 对电压跌落进行了补偿(single-phase AVQR for power quility improvement)

一个简单的UCOSII操作系统，在DE2上面调试通过(A simple UCOSII operating systems, debugging through the DE2 above)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

一个简单的总线bus代码，初学者可以借鉴学习-A simple bus-bus code, beginners can learn to learn

Library OLED SSD1305

cpu微命令vhdl源代码-cpu-order VHDL source code