VHDL语言实现时钟程序，用fpga开发板试过后，能够执行

摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL 语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。 关键词：CPLD；VHDL；交通灯控制器 中图分类号：TP39 Abstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by-Abstract: This paper introduces the CPLD chip to the traffic lights at the crossroads of design, traffic lights with CPLD as the master controller chip, the use of VHDL language control procedures, the use of CPLD re-programming and dynamic system reconfiguration in the features greatly enhance the digital system design flexibility and versatility. Keywords: CPLD VHDL traffic lights controller CLC number: TP39 Abstract: This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by

长帧同步时钟的产生， 源码程序，实验好用(Long frame synchronization clock generation, source program, easy to use experimental)

本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)

这是我们eda的课程大作业，用quartus仿真循环彩灯并下到板子里能完美的运行出四种波形。工程比较完整，希望对大家有帮助。

这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" script, useful for beginners, thank you! !

关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)

我是复旦的研究生。这是用VHDL写的ALU，仿真通过，压缩包里包括了每个源代码，而且都有相应的testbench，你直接加入你的工程当中就可以进行验证。设计时。我使用Modelsim环境来编写的。

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)

坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction