VHDL语言实现时钟程序，用fpga开发板试过后，能够执行

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

FPGA设计中的60进制计数器，通过2个七段数码管系那是出来。代码简单易懂，仿真通过，而且在FPGA开发板上加载显示成功。很有用的入门代码。

verilog 编写的比较最大值最小值得的程序，而且能够求出最大最小值在ram中存储的位置，测试通过下载即用(Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values ​ ​ can be obtained is stored in ram position, the test that is used by downloading)

verilog实现watch dog，可直接用于芯片开发中。(erilog realization watchdog, can be directly used for chip development.)

包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)

Xilinx Spartan-3E Starter Kit Board User Guide(中文用户手册)(Xilinx Spartan-3E Starter Kit Board User Guide)

2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)

VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report

用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，-CPLD driver speakers with music player, the program is written in VERILOG,