VHDL语言实现时钟程序，用fpga开发板试过后，能够执行

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

SCAS `89 基准电路下载，包括Verilog和VHDL格式。verilog格式30个文件：包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)

DE2-115开发板LED显示测试源码，对fpga开发者提供参考(DE2-115 development board LED display test source, provide a reference for fpga developer)

LPDDR2 SDRAM memories compliant to JEDEC JESD209-2.

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)

fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code

无线通信调制解调用的verlog和matlab程序，很大很实用。(Wireless modem calls verlog and matlab program, very very practical.)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)

IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)