VHDL语言实现时钟程序，用fpga开发板试过后，能够执行

对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)

64-point FFT/IFFT processor architecture : Rrdix-SDF

通信系统中的基带信号处理中的成型滤波器代码，已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)

vhdl code for internet interface

此程序为Verilog控制ADC的全部程序，已检验可以应用-This procedure for the Verilog control ADC all procedures can be applied to test

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

32位加法器作为VHDL编写的第一个代码；

Priority encoder in VHDL.

基于DE2的视频电话部分源码，实现了视频图像采集，VGA显示，局域网通讯等功能-DE2-based video telephony part of the source code to achieve the video image capture, VGA display, LAN communications function

本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。(Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.)