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Vhdl_testbench
vhdl 的testbench编写教程,英文ppt以及源码工程(Write tutorials, as well as English ppt Source of engineering vhdl testbench)
- 2016-08-29 10:09:05下载
- 积分:1
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clock
Quartus II软件设计数字电子钟,使用verilog语言编写各个
模块生成symbol files,再用原理图方式制作顶层文件。
完成的功能有:能够显示时、分、秒;具有清零,调节分钟的功能;
具有整点报时功能,声响电路发出叫声;
(failed to translate)
- 2013-05-07 10:11:31下载
- 积分:1
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DATA_Scramble
扰码器的FPGA实现,选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)
- 2021-01-16 19:28:46下载
- 积分:1
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Rotating coordinates high
高速计算机旋转坐标算法的硬件实现,用于快速傅里叶算法的核心单元-Rotating coordinates high-speed computer hardware algorithm for fast Fourier algorithm is the core unit
- 2022-02-16 05:47:02下载
- 积分:1
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can_latest.tar
用verilog编写的can总线控制器,包括设计参考历程和仿真程序,以及开发文档!(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)
- 2015-07-23 19:55:03下载
- 积分:1
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分:1
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vhdl_lms
vhdl 语言实现的lms算法的自适应滤波器 两种实现方式 包括改进(VHDL language lms algorithm adaptive filter implemented in two ways including improved)
- 2012-04-26 18:15:02下载
- 积分:1
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forug_2016.03
说明: formality2016 userguide
- 2019-10-29 14:59:40下载
- 积分:1
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系统设计
说明: 基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)
- 2020-06-21 02:20:01下载
- 积分:1
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last
verilog,FPGA的TDC电路设计(verilog ,TDC base on FPGA)
- 2021-01-04 18:48:54下载
- 积分:1