一个电子中的verilog实验源代码。适合verilog初学者学习参考

DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

ＶＨＤＬ编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.

基于FPGA/EP2c5的开发板详细例程，内容丰富，简单易懂(Development board based on more routine FPGA/EP2c5, content rich, easy to understand)

说明：  FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)

该源码用vhdl语言制作了一个简单的交通灯，方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

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H.264中二进制算术编码的硬件实现Binary arithmetic coding in H.264 hardware implementation(Binary arithmetic coding in H.264 hardware implementation)