MIPS32 的 ALU 设计

基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog

这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)

典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在project文件夹里面 3. 源文件和管脚分配在 tl文件夹里面 4. 下载文件在download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects project folder inside 3. the distribution of the source file and pin in rtl folder inside 4. download files in download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

采用倍频及1/3、1/12倍频绘制的路面不平度频谱图（自编）(Using octave and 1/3, 1/12 octave drawn road roughness spectrum (self))

可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)

说明：  quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

vhdl编程语言电子书，英文的，有很多例子(VHDL programming language e-books, in English, there are many examples of)