四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型...

移位除乘法器带testbench好用的工程(Useful addition to the shift multiplier works with testbench)

一个用verilog写的串行传输到并行传输的程序，在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters

用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！-Vhdl to do with the computer information on the composition of curriculum design principles to achieve the addition operation, a sum, simulation examples, etc.!

采用SG3525实现感应加热电源的频率跟踪。(SG3525 is used to realize frequency tracking of induction heating power supply.)

说明：  使用verilog实现ppm解码器，功能仿真通过，附设计说明，THU微纳电子系ic设计课大作业。(a ppm decoder written in VerilogHDL, a design document is available)

Digital Design and Modeling with VHDL and Synthesis

morris mano basic vhdl code in ise

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design

实现温度显示，接温度传感器。在4数码管上显示小数点后两位的温度(temperture of FPGA)

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)