四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型...

verilog编写的全功能串口-verilog programme of serial port

收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

verilog写的LnE算法，可用于计算指数和对数(Verilog written in LnE algorithm, can be used to calculate the index and the logarithm)

I2C MASTER DESIGNED by Verilog

交通灯控制（VHDL）-Traffic Light Control (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

说明：  RS(255,247)编码解码器Verilog源代码(Verilog source code of RS (255247) codec)

说明：  this code works with spi and uart interfaces.