四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型...

实现ITU-BT1120数字并行接口的编码和解码(decode and encode ITU-BT1120 parallel digital interface)

该源码为VHDL语言编写的分频器，在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated

这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

four bit counter verlog source code for veriwell including test bench

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

Complete Successive approximation Analog to digital converter along with the source code

一個紅外線感測電路的設計，是經由opa來設計。(An infrared sensing circuit design, is designed by opa.)

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

有一个 8 位全加器 VHDL 代码。我测试该代码在协同，看到了这段代码的工作。