可编程逻辑器件实验

基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

这是一个基于FPGA实现的GPS的程序，保证可以用-This is an FPGA-based GPS program to ensure that you can use ... ...

DDS的VHDL程序，相当好，值得下载，共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

ZardWars Files ------------------------------

本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 //制器，10个bit是1位起始位，8个数据位，1个结束 //位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 //现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是 //9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 //划分为8个时隙以使通信同步. //程序的工作过程是：串口处于全双工工作状态，按动key1，FPGA向PC发送“21 EDA" //字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA发送0-F的十六进制 //数据，FPGA接受后显示在7段数码管上。 //视频教程适合我们21EDA电子的所有学习板(this is a base vhdl for uart progarm.)

FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.

一个简单的23计数器，用VHDL实现，可供初学者学习。(A simple 23 counters, with the VHDL implementation, available for beginners.)