一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...

硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.

用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-VHDL language using a control program, the main function is to input code synchronization, and frame signals output word

verilog 写的 多功能数字钟-verilog to write multi-functional digital clock

verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package

说明：  there's a clock divider for DE2 altra board clock (50MHz)

Verilog for SPI Core source code

按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)

用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in