一种使用modelsim6简单的编码程序

VHDL描述的跑马灯程序，用于初学者练习-Marquee procedures described in VHDL, for beginners to practice

this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

Program to implement convolution of two signals.

system Verilog combinational logic

实施256点，

智能小车用到的c程序，单片机C语言与FPGA的 VHDL语言的结合(Smart car used c program, microcontroller C language and the combination of FPGA VHDL)

高性能FPGA应用领域及其研究，FPGA的开发流程-High-performance FPGA applications and research, FPGA development flow

尊敬的先生：，

matlab科斯塔斯环的仿真，有波形，很实用的程序(matlab costas m programm)