一种使用modelsim6简单的编码程序

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

说明：  VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file

说明：  win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)

processor design istruction load pipeline ,hazard

基于对ROM的编写，在quartusII上实现九九乘法器的实现，在试验箱的四个数码管上分别显示乘数，被乘数，积

温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)

verilog ADPLL file with testbench.v

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)