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频率计
说明: 1、能正确显示输入信号频率;
2、测量频率范围为1Hz ~ 999999Hz;
3、测量结果以十进制数字显示;
4、能测量幅值较小的信号频率;
5、有自动刷新输出数据的功能(如5s刷新一次);
6、有自检模块(如产生100Hz的校准方波);(1. It can correctly display the input signal frequency;
2. The frequency range of measurement is 1Hz ~ 99999hz;
3. The measurement results are displayed in decimal;
4. It can measure signal frequency with small amplitude;
5. It has the function of automatically refreshing the output data (e.g. once in 5S);
6. Self checking module (such as generating 100Hz calibration square wave);)
- 2020-03-28 16:37:56下载
- 积分:1
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用FPGA verilog hdl实现千兆以太网MAC。
用FPGA verilog hdl实现千兆以太网MAC。-Using FPGA verilog hdl realize Gigabit Ethernet MAC.
- 2022-05-10 18:11:05下载
- 积分:1
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FDPIM_Encode
关于语音通信信道调制的程序代码,是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分:1
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用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。...
用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分:1
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使用Veriolog hdl 编写手机屏测试程序.
使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.
- 2023-04-25 00:20:03下载
- 积分:1
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fsk调制与解调,此程序经过验证,可以运用,通讯方面的同学可以用...
fsk调制与解调,此程序经过验证,可以运用,通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
- 2022-01-26 06:28:59下载
- 积分:1
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4个7段lcd同时显示的程序,已经在digilent的nexy2板上通过验证,非常好用易懂,适合初学者学习...
4个7段lcd同时显示的程序,已经在digilent的nexy2板上通过验证,非常好用易懂,适合初学者学习-display 4 leds
- 2022-09-21 08:15:03下载
- 积分:1
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16QAM
基于FPGA 16QAM解调verilog代码,(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分:1
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The experimental results are used to prepare MOSIN6 is achieved Verilog HDL lang...
有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的:
1. 掌握条件语句在简单时序模块设计中的使用;
2. 学习在Verilog模块中应用计数器;
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的:
1. 通过实验,掌握阻塞赋值与非阻塞赋值的概念和区别;
2. 了解阻塞赋值与非阻塞赋值的不同使用场合;
3. 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi
- 2022-03-18 15:26:04下载
- 积分:1
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xiangmu_chengxu
雷达基本恒虚警处理,CA-CFAR(单元平均恒虚警处理),OS-CFAR(有序类恒虚警处理),SO-CFAR(选小类恒虚警处理),(radar basic constant alarm operation,obtaining os-cfar,so-cfar,os-cfar,ca-cfar)
- 2020-12-01 20:59:28下载
- 积分:1