system c 是在C环境下的硬件描述语言,比VHDL 等语言具有更强的抽象能力,内有system C的开发支持库和一些VC下的开发例程...

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL

test bench for alu 6 functions

this is a verilog code for root raised cosine filter

FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。 本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)

基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir

Kluwer academic the verilog hardware description language fith edition

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation

基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。(FPGA-based local bus interface. Based fifo contains two programs and the general register.)

vhdl 键盘程序，对键盘输入的字符进行判断，写入fpga中-VHDL key