赛灵思XC2C256频率计的Verilog实现。mt10t7 7

turbo码在LTE中的实现，并在fpga中得到了实现(turbo code in LTE implementations, and have been achieved in fpga)

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果(described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output)

一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly

32位加法器作为VHDL编写的第一个代码；

8位7段LED显示源码，扫描显示，稳定高效-seven of the eight LED source, scanning, stable and efficient

verilog 编写的比较最大值最小值得的程序，而且能够求出最大最小值在ram中存储的位置，测试通过下载即用(Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values ​ ​ can be obtained is stored in ram position, the test that is used by downloading)

本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。(I collected multiple VHDL language of sine wave generator SPWM program.)

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game

用VHDL语言实现TDMA编码,简单，明了。看标注就可以看懂-use vhdl langhanTDMA