赛灵思XC2C256频率计的Verilog实现。mt10t7 7

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理(11 order of fir digital filter verilog programming, linear phase, the coefficient quantization)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

本资源包括了加法器的VHDL代码实现，供大家学习。

非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation

占空比1：1的通用分频模块-1:1 generic-frequency module

DEBOUNCEfpga的实现，运用软件实现数码管的变化(fpga of the)

Matlab to hdl code for Least_square testbench

TI F28027 SCI 源码，中断，FIFO，LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)