赛灵思XC2C256频率计的Verilog实现。mt10t7 7

四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through

hdlc协议的封装与解析，fsc校验，完整的例程代码(Decode and Encode an HDLC packet ，using FCS16 calculation)

软件的使用程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,(very good)

清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。(Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.)

HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)

初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)

基于DE2-70开发板的VGA接口实现程序，可在VGA屏幕上显示800*600分辨率的图像，刷新频率60Hz

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

designing of 16 bit adder using 4 bit adder using verilog code

说明：  FSK VHDL FSK调制与解调VHDL程序及仿真(FSK VHDL )