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4x4 KEYPAD median counter input, input their own definition of the median
4X4 KEYPAD 的输入位数计数器,可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median
- 2022-01-27 22:09:15下载
- 积分:1
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波形发生器,带TESTBENCH,
多平台
波形发生器,带TESTBENCH,
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分:1
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8051 verilog achieve, enclosing testbench, c language debugging procedures
8051的verilog实现,内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
- 2022-10-21 05:35:03下载
- 积分:1
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AD9826-verilog
使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)
- 2016-05-09 14:45:37下载
- 积分:1
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1553B的编解码程序是有用的给大家分享分享
1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
- 2022-07-28 09:59:52下载
- 积分:1
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基于fpga和xinlinx ise的串行通信vhdl程序,希望对你有所帮助!
基于fpga和xinlinx ise的串行通信vhdl程序,希望对你有所帮助!-xinlinx and ideally serial communications VHDL process, and I hope to help you!
- 2023-05-29 05:45:03下载
- 积分:1
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简单的键盘接口模块程序
一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分:1
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用Verilog做的SD卡控制器(有详细的注释)
说明: SDIO 接口,实现SD卡的控制器功能,带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)
- 2020-06-16 22:00:01下载
- 积分:1
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vhdl学习程序
vhdl学习基本编写程序,关于温度的读取和显示,vhdl学习基本编写程序,关于温度的读取和显示,vhdl学习基本编写程序,关于温度的读取和显示
- 2022-02-03 11:27:12下载
- 积分:1
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ADc
与单片机相比,用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809,根据ADC0809的工作时序使用CPLD产生该控制信号,CPLD启动AD转换后,得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)
- 2021-03-29 11:19:10下载
- 积分:1