网站首页

登录

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...

于 2023-03-11 发布文件大小:376.91 kB

 0  146

下载积分: 2 下载次数: 1

我要下载

代码说明：

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

use of the VHDL language ALTERA company's board up3 have vga signal containi...
使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.

2022-01-31 21:08:09下载

积分：1
rs(31-19)
本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。(Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.)

2011-05-25 20:59:37下载

积分：1
dianzhen
如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

2014-01-16 16:13:53下载

积分：1
I121-v1.10
Implementation of Serial Infrared decoder for low-speed IrDA communications.

2013-06-14 05:38:14下载

积分：1
Verilog-learning-experience
初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

2013-09-30 09:51:04下载

积分：1
反设计的VHDL例子，使用QuickLogic ECLIPS
VHDL examples for counter design, use QuickLogic eclips

2022-08-25 05:17:29下载

积分：1
DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

2013-07-25 11:22:28下载

积分：1
vivado2018+IPs
说明： Xilinx Vivado 2018 License File

2021-01-19 22:08:41下载

积分：1
用可编程逻辑器件实现PWM波形即PWM波形发生器
用可编程逻辑器件实现PWM波形即PWM波形发生器-Using programmable logic devices that realize PWM waveform PWM Waveform Generator

2022-07-21 11:20:43下载

积分：1
ComChange-12061629
并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

2019-03-13 01:38:44下载

积分：1

696516资源总数
106914会员总数
0今日下载