DDR (double rate) SDRAM controller reference design Verilog code, can be directl...

Verilog-RISC CPU

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

2004 SNUG of systemverilog

一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl

用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!-VHDL language with the image sensor TCD132D realize the timing-driven code, timing accurate!

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)

URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)