DDR (double rate) SDRAM controller reference design Verilog code, can be directl...

说明：  利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)

直接序列扩频通信系统： 包含： 信源、扰码、交织、直扩、BPSK调制、解调、相关、解交织、解扰 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

四线电阻式触摸屏，ads7846控制显示触摸坐标(Four-wire Resistive Touch Panel, ads7846 touch control display coordinates)

上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners

Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)

说明：  多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

AHDL语言介绍，很详细的介绍AHDL语言介绍，很详细的介绍(AHDL language introduction, a detailed explanation)

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through

简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)