DDR (double rate) SDRAM controller reference design Verilog code, can be directl...

高性能FPGA应用领域及其研究，FPGA的开发流程-High-performance FPGA applications and research, FPGA development flow

该源码为VHDL语言编写的分频器，在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

说明：  自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

说明：  uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

RobustVerilog生成verilog工具(RobustVerilog version)

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written