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Altera-FPGA_CPLD-design-Advanced
《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性,LogicLock设计,时序约束,设计优化,高级工具及系统级设计技术,是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)
- 2017-03-08 19:47:32下载
- 积分:1
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一个可以综合的Verilog 写的FIFO存储器
内附文档说明
一个可以综合的Verilog 写的FIFO存储器
内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
- 2022-03-13 18:19:46下载
- 积分:1
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ADC_pf89
本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA,亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)
- 2020-11-28 13:09:30下载
- 积分:1
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traffic_lights
交通灯控制器控制红(r)、绿(g)、黄(y)三种不同颜色的交通灯,这三种不同颜色灯的亮、灭分别由三个定时器(timer1、timer2、timer3)控制;
当某个定时器工作时,它所控制的交通灯亮,直到设定的定时时间到(该定时器状态由’0’变’1’),交通灯跳转到另一种状态;
clk是脉冲控制端(图中未标出);reset是异步复位端,复位状态为红色交通灯亮;
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分:1
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temperature
温度传感器实验,将温控芯片的温度信号通过fpga用数码管显示(temperature display)
- 2012-03-26 21:49:23下载
- 积分:1
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AD6 中进行FPGA设计与仿真
说明: AD6 中进行FPGA设计与仿真,很不错的资料哦(FPGA design and Simulation in AD6, very good data)
- 2020-04-15 21:22:17下载
- 积分:1
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CCMU
代码是一个复数乘法器,两个复数相乘,只用到了2个实数相乘,运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)
- 2011-11-04 11:56:47下载
- 积分:1
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psk_rician-channel-MATLAB
QPSK在赖斯信道下的模拟仿真,包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)
- 2013-04-26 21:30:18下载
- 积分:1
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ram
代码实现了一个由32位寄存器组成的寄存器组,并有多个控制输入和两个输出,方便使用。(The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.)
- 2009-10-23 16:09:44下载
- 积分:1
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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分:1