JOP of RAM VHDL source code, classic classics, difficult to find a good price.

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一个双向总线的vhdl实现-a two-way bus VHDL achieve

使用matlab实现cdma 系统的rake接收机，比较最大比合并，等增益合并和选择性合并接收算法的性能(脢 鹿 脫脙matlab脢渭脧脰cdma 脧渭脥 鲁 渭脛rake 陆 脫脢脮 禄煤 拢 卢 卤 脠 陆 脧 脳 卯)

HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit

说明：  SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

matlab dsp building fpga(matlab dsp building )

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)