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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
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quartus2
quartus2的中文文档,不是很全,仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)
- 2010-07-29 19:49:52下载
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FM
说明: 使用Verilog HDL ,FM调制信号。(Using Verilog, HDL, and FM modulation signals.)
- 2017-10-09 22:35:11下载
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the CD
本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子,这些例子全部通过了验证。第七章以后的设计实例,不仅有Verilog-HDL的例子,也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。
-the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
- 2023-04-27 17:15:04下载
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16_QAM
用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)
- 2013-09-02 16:23:40下载
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vhdl
说明: 学习vhdl硬件描述语言的一些例子的原代码(VHDL hardware description language to learn some examples of the original code)
- 2008-11-11 20:45:37下载
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出租车计价器VHDL程序与仿真 的vhdl源代码
出租车计价器VHDL程序与仿真 的vhdl源代码-Taximeter VHDL procedures and simulation vhdl source code
- 2022-03-29 12:46:57下载
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通信基带信号发生器的设计,采用单片机输入频率和波形,在FPGA中实现频率和波形生成...
通信基带信号发生器的设计,采用单片机输入频率和波形,在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation
- 2022-03-14 12:44:53下载
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de2 vga controller board can also be used for other development
de2 vga控制器,也可用于其他板子开发-de2 vga controller board can also be used for other development
- 2022-05-17 01:30:37下载
- 积分:1