此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具

systemc实现的一个fifo，对想要学习systemc的同学很有帮助哦(A fifo systemc achieved, the students want to learn systemc helpful oh)

UVM 1.2 golden code, (code for UVM, )

Great guide for writing VHDL

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.

基于VHDL可编程BPSk调制教学~~~十分好用`~容易学会-VHDL-based programmable BPSk modulation of teaching is very good ~ ~ ~ `~ easy to learn to

用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system

基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)