此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具

4位ALU,有两个4位输入，4位输出实现逻辑运算和算术运算，逻辑与或非，加1，减1等等功能(4 ALU, logical and arithmetic operations)

实验一：QuartusⅡ原理图输入法设计与实现一：实验要求    ①：用逻辑门设计实现一个半加器，仿真验证其功能，并生成新         的半加器图形模块单元。    ②：用实验一生成的半加器模块和逻辑门设计实现一个全加器，仿真验证其功能，并下载到实验板测试，要求用拨码开关设定输入信号，发光二极管显示输出信号。    ③：用3线—8线译码器和逻辑门设计实现函数F，仿真验证其功能，下载到实验板测试。要求用拨码开关 设定输入信号，发光二极管显示输出信号。二：报告内容

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures

售货机-VHDL语言-已调试通过 真的很好用哦~适合一切学习EDA的初学者，能够让你轻松度过EDA课！~(Vending machine-VHDL language- has been really good with debugging by Oh ~ EDA for all beginners to learn, to let you easily through the EDA class! ~)

booth algotihm verilog design and test

说明：  用MATLAB设计及FPGA实现IIR滤波器的方法 摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波 器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于 四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。(Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.)

vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2

4b5b编码器实现，初学者资源，简单的逻辑电路实现(4b5b encoder implementation, resources for beginners)

利用GPIO口模拟I2C通信，驱动富士通MB85RC系列铁电存储器 ** 支持的型号：MB85RC64/64V,MB85RC128/128V,不支持MB85RC16/16V(The master inputs the device address word (8 bits) following the start condition, and then the slave outputs)