vhdl 语言代码多路复用器

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数字电路与逻辑设计实验编程，包含多功能电子钟程序，实用，简易(Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple)

wishbone接口的设计，在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)

数字电路课程设计，用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)

数字电路的设计。以软件方式实现硬件电路，功能强大，开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy. )

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

基于DSP28335的产生ADc采样的程序(Program for generating ADC sampling based on DSP28335)

lacp代码，可以参照学习Lacp协议的相关状态机等知识(LACP code, can refer to the relevant state machine learning knowledge of Lacp protocol)