vhdl 语言代码多路复用器

51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)

ATSHA204_S加密芯片资料，学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)

ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling

24位x24位的乘法器 十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)

说明：  vcs中文使用教程，帮助你快速入门Linux下的VCS操作(VCs Chinese tutorial to help you get started with VCs operation under Linux)

关于FPGA针对LCD资源配置，及相关电路层次关系(LCD FPGA)

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

VDHL的简单DEMO演示，有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

Xilinx Sysgen User Guide