内容1：哈尔滨工程大学信息与通信工程学院的课件

说明：  VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数 VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)

SCAS `89 基准电路下载，包括Verilog和VHDL格式。verilog格式30个文件：包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)

基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.

利 用 来 vhdl 设 计 p cm的 实 现-Vhdl design used for the realization of p cm

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller" s 8 Design and Implementation

基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga

MD5 算法在Xilinx FPGA上的实现，希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)

原创：cos函数和sin函数的VHDL实现，很实用(cos of the VHDL implementation)

１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners