交通灯控制（VHDL）！！！！！！！！！！！！！！！！！！！！！！！！！！…

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

该代码实现了IIC对24C02的读写，写采用页写的方式，读采用随机的方式。(This code implements the IIC on 24C02 read and write, write, write using the page mode, read random way.)

double edfe trigger d latch

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

its the vhdl stuff for ddr sdram controller nice one easily understandable

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

说明：  quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)

OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)

异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation

交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵，msgin为输入比特，msgout为交织输出比特，row和rol为交织器的行和列，可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵，再按照一定的方式输出为比特流数据